p1 = 0;//HAUPTPUNKTE
p2 = 0;//1 EBENE
p3 = 0;//2 EBENE

/*
// HAUPTPUNKT
menue XX = '4###FPGA/FPSoC Design Flow###prod_eda_fpga_classical_design.html?'+(++p1)+','+(p2=0)+','+(p3=0);
// .....1 EBENE
menue3 = '4###..Unterpunkt A###subureda.html?'+p1+','+(++p2)+','+(p3=0);
// ...............2 EBENE
menue5 = '4###........Subpunkt A###subureda.html?'+p1+','+p2+','+(++p3);
*/



menue1 = '2###Electronic System<br>Level Design###prod_eda_elec_under.html?'+(++p1)+','+(p2=0)+','+(p3=0);
	//menue2 = '3###System Modeling<br>& Simulation<br>Environment####'+p1+','+(++p2)+','+(p3=0);
	//menue3 = '4###Virtual Platform<br>Development &amp;<br>Automatic Model<br>Generation####'+p1+','+(++p2)+','+(p3=0);
menue2 = '2###FPGA<br>Design Flow###prod_eda_fpga.html?'+(++p1)+','+(p2=0)+','+(p3=0);
	menue3 = '2###FPGA<br>Programming in C###prod_eda_fpga_progC_under.html?'+p1+','+(++p2)+','+(p3=0);
	menue4 = '3###FPGA<br>Creation-<br>to-Realization###prod_eda_fpga_creation.html?'+p1+','+(++p2)+','+(p3=0);
	menue5 = '2###Classic FPGA<br>Design Flow###prod_eda_fpga_class.html?'+p1+','+(++p2)+','+(p3=0);
		menue6 = '3###Design<BR>Creation and<br>Management###prod_eda_fpga_classical_design.html?'+p1+','+p2+','+(++p3);
		menue7 = '1###Simulation###prod_eda_fpga_classical_simulation.html?'+p1+','+p2+','+(++p3);
		menue8 = '2###Advanced<br>Verification###prod_eda_fpga_classic_adver.html?'+p1+','+p2+','+(++p3);
		menue9 = '1###RTL Synthesis###prod_eda_fpga_classical_rtl.html?'+p1+','+p2+','+(++p3);
		menue10 = '3###Integrated<br>Design<br>Environment###prod_eda_fpga_classical_integrated.html?'+p1+','+p2+','+(++p3);
	menue11 = '3###Time Closure<br>FPGA Design<br>Flow###prod_eda_fpga_time.html?'+p1+','+(++p2)+','+(p3=0);
		menue12 = '2###Physical<br>Synthesis###prod_eda_fpga_time_physical.html?'+p1+','+p2+','+(++p3);
	menue13 = '4###Add-on<br>Solutions for<br>FPGA Design<br>Flow###prod_eda_fpga_add.html?'+p1+','+(++p2)+','+(p3=0);
		menue14 = '2###RTL Rule<br>Checking###prod_eda_fpga_add_rtl.html?'+p1+','+p2+','+(++p3);
		menue15 = '1###FPGA-on-Board###prod_eda_fpga_add_fpgaon.html?'+p1+','+p2+','+(++p3);
		menue16 = '2###IP Cores<br>for FPGA###prod_eda_fpga_add_ipcores.html?'+p1+','+p2+','+(++p3);
menue17 = '1###ASIC Design Flow###prod_eda_asic.html?'+(++p1)+','+(p2=0)+','+(p3=0);
	menue18 = '2###Classic ASIC<br>Design Flow###prod_eda_asic_class.html?'+p1+','+(++p2)+','+(p3=0);
		menue19 = '3###Design<br>Creation and<br>Management###prod_eda_asic_classical_design.html?'+p1+','+p2+','+(++p3);
		menue20 = '1###Simulation###prod_eda_asic_classical_simulation.html?'+p1+','+p2+','+(++p3);
		menue21 = '2###Advanced Verification###prod_eda_asic_classical_adver.html?'+p1+','+p2+','+(++p3);
		menue22 = '1###RTL Synthesis###prod_eda_asic_classical_rtl.html?'+p1+','+p2+','+(++p3);
	menue23 = '3###Add-on Solutions<br>for ASIC<br>Design Flow###prod_eda_asic_add.html?'+p1+','+(++p2)+','+(p3=0);
		menue24 = '2###IP Cores<br>for ASIC###prod_eda_asic_add_ipcores.html?'+p1+','+p2+','+(++p3);
				

menue25 = '3###High Level<br>Verification<br>Solutions###prod_eda_high.html?'+(++p1)+','+(p2=0)+','+(p3=0);
	menue26 = '2###Advanced Verification###prod_eda_high_adver.html?'+p1+','+(++p2)+','+(p3=0);
	

menue27= '2###Signal Integrity<br>Solutions###prod_eda_signal.html?'+(++p1)+','+(p2=0)+','+(p3=0);
menue28 = '1###PCB Design Flow###prod_eda_pcb.html?'+(++p1)+','+(p2=0)+','+(p3=0);
menue29 = '2###Trainings<br>and Seminars###prod_eda_trainings.html?'+(++p1)+','+(p2=0)+','+(p3=0);


var anzahl_punkte = 29;